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The G-7802C Serial-to-Parallel, FS Receiver has a 3-frequency, frequency-shift receiver with a carrier detector for generating the data and synchronizing bits from the incoming tones. The decoder section reconstructs the 16-bit parallel output from the serial data stream. These outputs are buffered to a 12 volt CMOS level.
The FS receiver generates a data pulse stream which contains the 16 bits of information with bit 17 as the parity bit. The receiver also generates a sync pulse that synchronizes the starting of a new data word. The sync pulse performs the task of starting the local clock at the beginning of the data stream. The sync pulse also loads the clocked-in serial data to the parallel outputs of the shift registers.
A parity check is performed on the incoming data stream and the resulting parity bit is compared with the incoming parity bit. If the two do not agree, the center-bit pulse is not allowed to update the parallel outputs of the shift register. If double scan check is enabled by J3, as the second scan of information comes in, it is compared with the bits shifted out of the shift register. In an ideal condition the two streams should match. If the two do not match, again the outputs of the shift registers are not updated. If a carrier loss is detected by the carrier detector in the FS section, then the output buffers are not enabled and the outputs of the module remain the same. This system of checks provides for very secure and noise immune communication of the 16-bit message from the G-7801C Parallel-to-Serial Transmitter.
A Divider after the clock allows the bits-per-second to be selected by a solderless jumper. There are possible rates of 30, 60, 120, 240, and 480 bits-per-second. The channel bandwidth typically required is numerically twice that of the bits-per-second rate. A G-7802C-E is available to extend the data message to 32 status outputs.
Specifications
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